netrashetty
Netra Shetty
Amkor Technology, Inc. (NASDAQ: AMKR) is a high-tech semiconductor product manufacturer that includes Intel and IBM among its primary customers. Previously headquartered in West Chester, Pennsylvania, United States, Amkor announced on June 3, 2005, that it had moved to Chandler, Arizona.[4] The company has 20,033 employees worldwide and had $1.9 billion in sales in 2004.
With the majority of its factories in China, Japan, Korea, Philippines, Singapore, Taiwan, and the United States, Amkor is a leading player in the semiconductor industry. It packages and tests integrated circuits (ICs) for chip manufacturers. One of Amkor's product developments is its MicroLeadFrame chip carrier (IC package) technology.
Amkor Technology, Inc. (AMKR) is one of the largest subcontractors providing backend services to semiconductor manufacturers and electronics OEMs. The company is based in Chandler, Arizona, with 5.6 million square feet of manufacturing facilities, product development centers and sales and support offices across China, Japan, Korea, the Philippines, Singapore, Taiwan and the U.S. The subcontracting market has been growing over the past few decades, as OEMs increasingly outsourced portions of their manufacturing in order to meet escalating demand. In recent times, this has also become a necessity on cost considerations, as the sophisticated infrastructure required for manufacture is also very expensive.
Semiconductor manufacturing consists of front-end and back-end operations. The device formation stage is referred to as the front-end operation. This process begins with a wafer (usually made of silicon) having a layer of photoresist (a chemical that hardens when exposed to an ultraviolet light source) spin-coated onto the surface in liquid form. After the excess solvent is driven off, the wafer is "soft-baked" or cured. A photomask is then loaded into the lithography system. An excimer laser is passed over the photomask and through a reduction lens system that exposes the desired areas of photoresist, which is subsequently removed, permitting deposition to the surface of the wafer. A strip system is utilized to remove the photoresist or other chemical residues following diffusion processing or film deposition. Thin layers of dopants are then grown or deposited in a precise pattern within the wafer using various chemical, vapor or ion implant techniques. The deposition process alters the atomic structure of the material, and therefore, necessarily, the electronic properties of the material. Further into the wafer fabrication process, a series of metallization steps are executed, in which conducting materials, that interconnect the semiconductor devices, are deposited. Multiple layers of conducting, semiconducting and insulating materials are constructed on and within the wafer via successive steps of lithography, etching and deposition, utilizing unique masks for each layer. Depending on the geometry and the device, anywhere from 35 to 45 unique masks are used in the device formation process with 10 to 100 layers (or more for microprocessors) being constructed. Typically, the outcome is a wafer with multi-layered semiconducting devices, known as transistors. The transistors are interconnected with conducting materials, and insulating materials are used to electronically isolate the active components. The net result is a silicon wafer that contains multiple copies of integrated circuit devices.
The back-end of the manufacturing process takes place after a wafer has completed the device formation stage in which multiple copies of an IC have been constructed on a single wafer. A wafer prober then moves the wafer so that each die's (IC device) electrical contact points are properly aligned with the probe card's pins, facilitating the parametric or functional testing of the device. Parametric testing is done both during and at the completion of the device fabrication process. Functional testing, completed after final construction, determines whether the device meets performance specifications (wafer sorting). Following the wafer sort, the wafer is cut into individual die. Each die has electrical leads attached and then packaged within an environmentally protective encasement. The purpose of the die package or encasement is to protect the semiconductor device from environmental elements and secure the electrical contacts to the protruding electrical leads. In addition, the encasement acts as a medium though which thermal energy or heat is dissipated from the die. A final test is then conducted on the chip. Wafer probers are used in wafer sorting applications roughly 85% of the time, while the rest are used in parametric testing. Thus, most of the testing is done in the back-end of the fabrication process.
The first step in the packaging process is called backgrinding, which scrapes off the back side of the chip, thus making it thinner. Modern devices have increased the demand for thinner chips. Consequently, the acceptable wafer thickness today is around 8-20mm. The wafer, along with its plastic or metal frame is then mounted on a dicing tape, the excess tape being cut off. The individual chips are cut according to programmed dimensions using a resin-bonded diamond wheel, and cleaned. After mounting and wafer sawing, the chips are soldered to lead frames. Although leadframe packaging is the traditional method of packaging, the process has undergone some changes over the years. The lead frame is a 0.5-3.0-inch strip of copper or copper alloy, coated with metals such as tin or lead alloys, pure tin or silver. The chip is mounted onto the lead frame for soldering, which is also designed to form leads after the final encapsulation of the product. The soldering surface of the chip is treated before mounting, since silicon dioxide on the chip surface inhibits the adhesion of metals. It is coated with metal and treated with hydrofluoric acid (etching). Hydrofluoric acid combines with the silicon dioxide and releases water. After washing, the surface is sputtered with a metal (usually titanium), which consumes any remaining silicon dioxide. The titanium is layered with copper or nickel, followed by protective layers of flash gold, palladium or silver. Soldering is a three-step process, involving the deposition of soldering paste on the lead frame substrate, mounting the die on the substrate and reflowing the soldering material over the chip. Care is taken to prevent the formation of gaps or voids in the soldering, as this could lead to contamination of the chip. The soldered chip is connected to the system board with the help of the leads on the perimeter of the package. This is followed by wire bonding, a process in which gold/aluminum/copper wires are used to provide an electrical connection between the silicon chip and metal leads. The die are then coated either selectively or wholly with a moisture-resistant material (usually silicon) in such a way that the wires remain exposed. This coating reduces package stresses and possible corrosion of the die. This process is followed by molding or plastic coating, sealing and marking. The excess plastic is cut off and the leads are trimmed and shaped. The final process is leadfinish, which is the application of a coat of metal over the leads to protect them against corrosion and abrasion, and improve their solderability and appearance.
Amkor has leveraged its leadframe packaging capabilities to offer multi-chip and stacked die plastic packaging in the form of TSOP, TSSOP, SSOP, LQFP, PLCC, MQFP, MicroLeadFrame, SOIC, PDIP and ExposedPad. Some of its other packaging capabilities include wafer level packaging (WLP), chip scale packaging (CSP), ball grid array (BGA, PBGA and CBGA) packages, system in package (SiP), quad packages (LQFP, MQFP, PLCC, TQFP), image sensor/optical packages and ceramic packages. Ball grid array (BGA) is a more advanced form of packaging, where solder balls are used in place of electrical leads. The solder balls are made from plastic (PBGA) or ceramic (CBGA) that fit into specific positions on the printed circuit boards. They have more area for electronic connections, and allow better dissipation of heat from the device and lower distortion of signals, although their typical lack of flexibility make solder joints more prone to cracking.
Amkor's test services include wafer probe, final test, strip test, marking, baking, tape and reel, and drop shipment to final users, as directed by customers. The company is able to test almost all categories of integrated circuits, such as digital, linear, mixed signal, memory, radio frequency and any combinations of these.
Packaging and test are Amkor's two reporting segments. Packaging generated the bulk of revenue (90%) in 2006, while test accounted for the remaining 10%. Approximately 8.8 billion units were processed by the company in 2006. Management estimates that the chips passing through its factories were primarily used in the communications, consumer, computing and other end markets. These end markets accounted for 37%, 26%, 26% and 11% of its 2006 revenue, respectively.
Amkor's most important customers include Altera, Atmel, Conexant, Freescale Semiconductor, Intel Corporation, IBM Samsung Electronics, ST Microelectronics, Texas Instruments and Toshiba Corporation. No customer accounted for more than 10% of revenue in fiscal 2006.
With the majority of its factories in China, Japan, Korea, Philippines, Singapore, Taiwan, and the United States, Amkor is a leading player in the semiconductor industry. It packages and tests integrated circuits (ICs) for chip manufacturers. One of Amkor's product developments is its MicroLeadFrame chip carrier (IC package) technology.
Amkor Technology, Inc. (AMKR) is one of the largest subcontractors providing backend services to semiconductor manufacturers and electronics OEMs. The company is based in Chandler, Arizona, with 5.6 million square feet of manufacturing facilities, product development centers and sales and support offices across China, Japan, Korea, the Philippines, Singapore, Taiwan and the U.S. The subcontracting market has been growing over the past few decades, as OEMs increasingly outsourced portions of their manufacturing in order to meet escalating demand. In recent times, this has also become a necessity on cost considerations, as the sophisticated infrastructure required for manufacture is also very expensive.
Semiconductor manufacturing consists of front-end and back-end operations. The device formation stage is referred to as the front-end operation. This process begins with a wafer (usually made of silicon) having a layer of photoresist (a chemical that hardens when exposed to an ultraviolet light source) spin-coated onto the surface in liquid form. After the excess solvent is driven off, the wafer is "soft-baked" or cured. A photomask is then loaded into the lithography system. An excimer laser is passed over the photomask and through a reduction lens system that exposes the desired areas of photoresist, which is subsequently removed, permitting deposition to the surface of the wafer. A strip system is utilized to remove the photoresist or other chemical residues following diffusion processing or film deposition. Thin layers of dopants are then grown or deposited in a precise pattern within the wafer using various chemical, vapor or ion implant techniques. The deposition process alters the atomic structure of the material, and therefore, necessarily, the electronic properties of the material. Further into the wafer fabrication process, a series of metallization steps are executed, in which conducting materials, that interconnect the semiconductor devices, are deposited. Multiple layers of conducting, semiconducting and insulating materials are constructed on and within the wafer via successive steps of lithography, etching and deposition, utilizing unique masks for each layer. Depending on the geometry and the device, anywhere from 35 to 45 unique masks are used in the device formation process with 10 to 100 layers (or more for microprocessors) being constructed. Typically, the outcome is a wafer with multi-layered semiconducting devices, known as transistors. The transistors are interconnected with conducting materials, and insulating materials are used to electronically isolate the active components. The net result is a silicon wafer that contains multiple copies of integrated circuit devices.
The back-end of the manufacturing process takes place after a wafer has completed the device formation stage in which multiple copies of an IC have been constructed on a single wafer. A wafer prober then moves the wafer so that each die's (IC device) electrical contact points are properly aligned with the probe card's pins, facilitating the parametric or functional testing of the device. Parametric testing is done both during and at the completion of the device fabrication process. Functional testing, completed after final construction, determines whether the device meets performance specifications (wafer sorting). Following the wafer sort, the wafer is cut into individual die. Each die has electrical leads attached and then packaged within an environmentally protective encasement. The purpose of the die package or encasement is to protect the semiconductor device from environmental elements and secure the electrical contacts to the protruding electrical leads. In addition, the encasement acts as a medium though which thermal energy or heat is dissipated from the die. A final test is then conducted on the chip. Wafer probers are used in wafer sorting applications roughly 85% of the time, while the rest are used in parametric testing. Thus, most of the testing is done in the back-end of the fabrication process.
The first step in the packaging process is called backgrinding, which scrapes off the back side of the chip, thus making it thinner. Modern devices have increased the demand for thinner chips. Consequently, the acceptable wafer thickness today is around 8-20mm. The wafer, along with its plastic or metal frame is then mounted on a dicing tape, the excess tape being cut off. The individual chips are cut according to programmed dimensions using a resin-bonded diamond wheel, and cleaned. After mounting and wafer sawing, the chips are soldered to lead frames. Although leadframe packaging is the traditional method of packaging, the process has undergone some changes over the years. The lead frame is a 0.5-3.0-inch strip of copper or copper alloy, coated with metals such as tin or lead alloys, pure tin or silver. The chip is mounted onto the lead frame for soldering, which is also designed to form leads after the final encapsulation of the product. The soldering surface of the chip is treated before mounting, since silicon dioxide on the chip surface inhibits the adhesion of metals. It is coated with metal and treated with hydrofluoric acid (etching). Hydrofluoric acid combines with the silicon dioxide and releases water. After washing, the surface is sputtered with a metal (usually titanium), which consumes any remaining silicon dioxide. The titanium is layered with copper or nickel, followed by protective layers of flash gold, palladium or silver. Soldering is a three-step process, involving the deposition of soldering paste on the lead frame substrate, mounting the die on the substrate and reflowing the soldering material over the chip. Care is taken to prevent the formation of gaps or voids in the soldering, as this could lead to contamination of the chip. The soldered chip is connected to the system board with the help of the leads on the perimeter of the package. This is followed by wire bonding, a process in which gold/aluminum/copper wires are used to provide an electrical connection between the silicon chip and metal leads. The die are then coated either selectively or wholly with a moisture-resistant material (usually silicon) in such a way that the wires remain exposed. This coating reduces package stresses and possible corrosion of the die. This process is followed by molding or plastic coating, sealing and marking. The excess plastic is cut off and the leads are trimmed and shaped. The final process is leadfinish, which is the application of a coat of metal over the leads to protect them against corrosion and abrasion, and improve their solderability and appearance.
Amkor has leveraged its leadframe packaging capabilities to offer multi-chip and stacked die plastic packaging in the form of TSOP, TSSOP, SSOP, LQFP, PLCC, MQFP, MicroLeadFrame, SOIC, PDIP and ExposedPad. Some of its other packaging capabilities include wafer level packaging (WLP), chip scale packaging (CSP), ball grid array (BGA, PBGA and CBGA) packages, system in package (SiP), quad packages (LQFP, MQFP, PLCC, TQFP), image sensor/optical packages and ceramic packages. Ball grid array (BGA) is a more advanced form of packaging, where solder balls are used in place of electrical leads. The solder balls are made from plastic (PBGA) or ceramic (CBGA) that fit into specific positions on the printed circuit boards. They have more area for electronic connections, and allow better dissipation of heat from the device and lower distortion of signals, although their typical lack of flexibility make solder joints more prone to cracking.
Amkor's test services include wafer probe, final test, strip test, marking, baking, tape and reel, and drop shipment to final users, as directed by customers. The company is able to test almost all categories of integrated circuits, such as digital, linear, mixed signal, memory, radio frequency and any combinations of these.
Packaging and test are Amkor's two reporting segments. Packaging generated the bulk of revenue (90%) in 2006, while test accounted for the remaining 10%. Approximately 8.8 billion units were processed by the company in 2006. Management estimates that the chips passing through its factories were primarily used in the communications, consumer, computing and other end markets. These end markets accounted for 37%, 26%, 26% and 11% of its 2006 revenue, respectively.
Amkor's most important customers include Altera, Atmel, Conexant, Freescale Semiconductor, Intel Corporation, IBM Samsung Electronics, ST Microelectronics, Texas Instruments and Toshiba Corporation. No customer accounted for more than 10% of revenue in fiscal 2006.