Description
Six Sigma at National Semiconductor
6 SIGMA AT NATIONAL SEMICONDUCTOR
Semiconducor Fabrication
? One of the most complex processes
? Involves nearly 200 steps on 75 pieces of
equipment ? Yields vary from as low as 40% for complex processes to 100% for less complex parts ? National Semiconductor’s (NS) defect rate <20ppm, yet they want to improve
How National Semiconductor Did It…
Define
? Fab failing at the final electrical test
? Failure attributed to current leakage at the
transistor level and gate oxide breakdown ? Baseline Yield improvement set at 1.5% ? Savings of more than $1 million
Measure
? Pareto chart of the reason of failures used
? Three process modules showed excessive
variation:
? Spacer formulation
? Channel Implants ? Post Implant Acid Cleaning
? Other suspected areas eliminated
Analyze
? Seven factors determined to have an impact on the 3 failure modes
? Three experiments developed to study their
impact on yield ? Design of Experiments (DoE) function of JMP statistical software used
? DOE 1--Transistor leakage between drain and
source
? Failure Modes: Silicon impurities, threshold voltage
control, physical damage ? Factors: VTN implant, spacer dep, spacer clean, spacer etch
? DOE 2--P channel contact leakage
? Failure Modes: Fixed charge, silicon impurities ? Factors: Post-poly SC1 cleans, HCL:H2O2 clean
? DOE 3--Gate breakdown voltage
? Failure Modes: Plasma budget, silicon impurities ? Factors: Alloy, spacer dep, spacer etch
Improve
? Certain Fabrication parameters were identified for improvement before DoEs
? DoE results helped in validation of these
actions ? Results of DoEs leveraged to make changes to specs, procedures and equipment ? Yield during the electrical test stage improved
Control
? Control plan formulated and transferred to mfg group
? Control plan defined requirements for all
critical parameters ? Control Charts, Control Limits, Sampling plans and out-of-control action plans
What did it achieve?
? Project lasted 9 months
? Initial goal was surpassed ? Yield increased by > 1.5% ? Savings of more than $1 Million ? National Semiconductor gained competitive
advantage ? 52 projects have been completed with an 84percent success rate
Thank You !!!
doc_991368902.pptx
Six Sigma at National Semiconductor
6 SIGMA AT NATIONAL SEMICONDUCTOR
Semiconducor Fabrication
? One of the most complex processes
? Involves nearly 200 steps on 75 pieces of
equipment ? Yields vary from as low as 40% for complex processes to 100% for less complex parts ? National Semiconductor’s (NS) defect rate <20ppm, yet they want to improve
How National Semiconductor Did It…
Define
? Fab failing at the final electrical test
? Failure attributed to current leakage at the
transistor level and gate oxide breakdown ? Baseline Yield improvement set at 1.5% ? Savings of more than $1 million
Measure
? Pareto chart of the reason of failures used
? Three process modules showed excessive
variation:
? Spacer formulation
? Channel Implants ? Post Implant Acid Cleaning
? Other suspected areas eliminated
Analyze
? Seven factors determined to have an impact on the 3 failure modes
? Three experiments developed to study their
impact on yield ? Design of Experiments (DoE) function of JMP statistical software used
? DOE 1--Transistor leakage between drain and
source
? Failure Modes: Silicon impurities, threshold voltage
control, physical damage ? Factors: VTN implant, spacer dep, spacer clean, spacer etch
? DOE 2--P channel contact leakage
? Failure Modes: Fixed charge, silicon impurities ? Factors: Post-poly SC1 cleans, HCL:H2O2 clean
? DOE 3--Gate breakdown voltage
? Failure Modes: Plasma budget, silicon impurities ? Factors: Alloy, spacer dep, spacer etch
Improve
? Certain Fabrication parameters were identified for improvement before DoEs
? DoE results helped in validation of these
actions ? Results of DoEs leveraged to make changes to specs, procedures and equipment ? Yield during the electrical test stage improved
Control
? Control plan formulated and transferred to mfg group
? Control plan defined requirements for all
critical parameters ? Control Charts, Control Limits, Sampling plans and out-of-control action plans
What did it achieve?
? Project lasted 9 months
? Initial goal was surpassed ? Yield increased by > 1.5% ? Savings of more than $1 Million ? National Semiconductor gained competitive
advantage ? 52 projects have been completed with an 84percent success rate
Thank You !!!
doc_991368902.pptx