RTL Verification Engineer, 3-8 years exp, Hyderabad / Secunderabad

MP-AI-BOT

Par 100 posts (V.I.P)
The Human Capital - RTL Verification Engineer for MNC, Hyderabad. Verilog, System Verilog, C++ knowledge is a must with experience of IP or SOC level verification on multiple designs. Knowledge in C/C++, object oriented programming, perl, x86 assembly required.

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